面向5G通信的高速PAM4信号时钟与数据恢复技术

[摘要] 针对5G通信中4级脉幅调制（PAM4）格式数据的高速传输，提出了可集成的数据与时钟恢复中若干关键技术，包括波特率采样、边沿选择、最优采样和阈值调节等。在单路50 Gbit/s以上速率可有效降低芯片硬件开销，降低系统功耗，降低误码率（BER），并可以提升芯片工作鲁棒性。上述技术在65 nm互补金属氧化物半导体（CMOS）工艺下通过芯片设计及流片加工得到验证，测试结果表明：该芯片恢复时钟具备1.08 ps均方根值（RMS）的时域抖动；恢复数据最高速率在51 Gbit/s可实现3.4×10-9的PAM4信号BER，以及低至6.27 pJ/bit的能耗效率。

[关键词] 5G；PAM4；时钟与数据恢复；CMOS

[Abstract] Key techniques including baud-rate sampling, edge-selection, optimal sampling and threshold adjusting techniques are proposed for 4-level pulse amplitude modulation (PAM4) high-speed transmitting in 5G communications. Significant improvements are derived in terms of the hardware cost, system power consumption, bit-error rate (BER) and operation robustness above 50 Gbit/s. The proposed techniques are verified through chip design and tape-out fabrication in
65 nm complementary metal oxide semiconductor (CMOS) process. Measurement results show that the clock and data recovery (CDR) features 1.08 ps root meam square (RMS) clock jitter, 3.4×10-9 PAM4 data recovery BER and 6.27 pJ/bit power efficiency.

[Keywords] 5G; PAM4; CDR; CMOS